1/5/10Pcs Micron MT48LC4M32B2P-7 SDRAM 128M (4M x 32) 143 MHz 3-3.6V TSOP-86

Description

1/5/10pcs Micron MT48LC4M32B2P-7 SDRAM 128M (4 M x 32) DRAM 143 MHz 3-3.6V TSOP-86
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with asynchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4096 rows by 256 columns by 32 bits.  Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[11:0] select the row).The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randomaccess operation. The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. The devices offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.
SPECIFICATIONS
Manufacturer: Micron Technology
Part Number: MT48LC4M32B2P-7 IT:G / MT48LC4M32B2 / MT48LC4M32B2P-7
Product Category: DRAM
Type: SDRAM
Mounting Style: SMD/SMT
Package / Case: TSOP-86
Data Bus Width: 32 bit
Organization: 4 M x 32
Memory Size: 128 Mbit
Maximum Clock Frequency: 143 MHz
Supply Voltage - Max: 3.6 V
Supply Voltage - Min: 3 V
Minimum Operating Temperature: - 40 C
Maximum Operating Temperature: + 85 C
Series: MT48LC
Moisture Sensitive: Yes
Subcategory: Memory & Data Storage
FEATURES
PC100-compliant
Fully synchronous; all signals registered on positive edge of system clock
Internal pipelined operation; column address can be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto precharge and auto refresh modes
Self refresh mode (not available on AT devices)
Auto refresh
– 64ms, 4096-cycle refresh (commercial and industrial)
– 16ms, 4096-cycle refresh (automotive)
LVTTL-compatible inputs and outputs
Single 3.3V ±0.3V power supply
Supports CAS latency (CL) of 1, 2, and 3
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